In a fabrication of semiconductor devices, IC designs are frequently required to meet manufacturing constraints to achieve an acceptable manufacturing yield. Accordingly, when such constraints are not met, traditional methods initiate a manual modification, which is an expensive and time consuming task, or utilize an automated engineering change order (ECO). However, automated ECO methods frequently rip-up a net and re-route, which in many cases, results even more violations of manufacturing constraints. Additionally, automated ECO may modify or displace standard-cells, thereby causing violations of manufacturing constraints. Further, such automated methods may never converge to a feasible solution and may have a large effect on timing and signal integrity, thereby resulting in even further violations of manufacturing constraints.
A need therefore exists for methodologies and apparatus for automated pattern-based semiconductor design layout correction.